Dies used in integrated circuits, such as memory circuits, may have several billion components fabricated thereon. For example, a memory circuit that is capable of storing one gigabit of data needs to have one billion individual storage components, such as gates or other devices. In order to make the dies, masks or reticles are made that include all the components that are to be located on the dies. The reticles may also include information necessary to complete processes in the fabrication of the die, such as plating. Therefore, several reticles may be required in order to fabricate a single die.
With so many components fabricated on a die, the reticles have to be very dense and contain a tremendous amount of information. In order to achieve the density required to make memory circuits and other high density dies, specialized machines are used to make the reticles. The desired layout of a reticle is encoded in a computer program that is used by the machines to make the reticle. When a reticle is required to contain billions of components, the computer program used to generate the mask is extremely complex and may have errors. Accordingly, the reticle will likely have errors.
The complexity of the reticles causes other problems. For example, a die may have many thousands of memory instances. These instances have to be put in different orientations in order for them to fit onto the die. Butterflying and mirroring are used in placing these thousands of instances. Often, the documentation associated with the placement of the instances on the reticles is not properly updated, which leads to an unknown physical to logical mapping of the components.
After a reticle is made, a limited number of dies are fabricated using the reticle in order to test the reticle for errors. The dies fabricated using the reticles are then tested for errors. In the case of memory circuits, the dies may be powered up and have data written to and read from the memory addresses to determine if all the electronic components corresponding to the memory addresses are functioning correctly.
If a memory address is found to be faulty, the die must be analyzed to determine the cause of the fault in order to further determine if the reticle is faulty. However, with so many extremely small components located on a die, it is very time consuming to locate a faulty component. In many situations, physically locating the components corresponding to a faulty address may take hundreds of man hours, which significantly delays production of the integrated circuits. Accordingly, conventional methods of confirming the logical to physical mapping techniques, such as laser induced defects, are not feasible on these complex dies.